Clocked half-rail differential logic

ABSTRACT

Clocked half-rail differential logic circuits are activated by a delayed clock. According to the invention, when clocked half-rail differential logic circuits of the invention are cascaded together, a delayed clock is provided for each clocked half-rail differential logic circuit and each delayed clock is timed to at least the delay of the previous clocked half-rail differential logic circuit. Consequently, according to the invention, a delay time is introduced to ensure each clocked half-rail differential logic circuit of the invention is switched or “fired” only after it has received an input from the previous clocked half-rail differential logic circuit stage. According to the invention, this is achieved without the use of complicated control circuitry.

FIELD OF THE INVENTION

[0001] The present invention relates generally to logic circuits and,more particularly, to half-rail logic circuits.

BACKGROUND OF THE INVENTION

[0002] With the emergence of an electronics market that stressesportability, compact size, lightweight and the capability for prolongedremote operation, a demand has arisen for low power circuits andsystems. This demand has motivated circuit designers to depart fromconventional circuit designs and venture into more power efficientalternatives. As part of this effort, half-rail differential logic hasemerged as an important design tool for increasing power efficiency.

[0003]FIG. 1 shows a prior art half-rail differential logic circuit 100Aand associated prior art control circuit 100B as was set forth in FIG. 1of the 1997 IEEE International Solid-State Circuits Conference PaperISSC97/SESSION 25/PROCESSORS AND LOGIC/PAPER 25.6 (hereinafter referredto as the ISSC97 PAPER 25.6). ISSC97 PAPER 25.6 is co-authored by theInventor of the present invention and is incorporated herein, byreference, for all purposes.

[0004] As seen in FIG. 1 of the present invention, prior art half-raildifferential logic circuit 100A included eight transistors, PFET 101,PFET 105, PFET 107, NFET 109, NFET 115, NFET 117, NFET 121, and NFET125. Prior art half-rail differential logic circuit 100A also includeddifferential logic 123 with inputs 151 and 153, output 111 and output113.

[0005] As discussed below, prior art half-rail differential logiccircuit 100A also required control circuit 100B. Control circuit 100Bincluded six transistors: PFET 129; NFET 131; NFET 133; PFET 137; PFET135 and NFET 139. Prior art control circuit 100B also included an enableout signal (eout) at terminal 143 and an enable out bar signal({overscore (eout)}) at terminal 141. According to the prior art, thecontrol signals eout and {overscore (eout)}, at terminals 143 and 141,respectively, were supplied to prior art half-rail differential logiccircuit 100A as control signals ein and {overscore (ein)} as discussedbelow.

[0006] As discussed above, prior art half-rail differential logiccircuit 100A required an enable in (ein) signal, coupled to the gate ofNFET 121 and NFET 125, and an enable in bar signal ({overscore (ein)}),coupled to the gate of NFET 101. The control signals ein and {overscore(ein)} were supplied by prior art control circuit 100B from terminals143 and 141, respectively. When multiple prior art half-raildifferential logic circuits 100A were cascaded together, prior artcontrol circuit 100B and control signals ein and {overscore (ein)} werenecessitated to ensure that each prior art half-rail differential logiccircuit 100A switched or “fired” only after it had received an inputfrom the previous stage.

[0007] Cascading is well known in the art. For a more detaileddiscussion of the cascading of prior art half-rail differential logiccircuits 100A, and the operation of prior art half-rail differentiallogic circuit 100A and prior art control circuit 100B, the reader isreferred to the ISSC97 PAPER 25.6 discussed above. A more detaileddiscussion of the operation of prior art half-rail differential logiccircuit 100A and prior art control circuit 100B is omitted here to avoiddetracting from the invention.

[0008] As noted above, when multiple prior art half-rail differentiallogic circuits 100A were cascaded together, each prior art half-raildifferential logic circuit 100A required prior art control circuit 100Bto ensure that each prior art half-rail differential logic circuit 100Aswitched or “fired” only after it had received an input from theprevious stage. However, prior art control circuit 100B was extremelycomplex, requiring at least six additional transistors and severalcircuit lines. Consequently, prior art half-rail differential logiccircuit 100A required significant addition components and space. This,in turn, meant that prior art half-rail differential logic circuit 100Arequired more silicon, a more complex design and more components topotentially fail. In addition, prior art control circuit 100B not onlyadded complexity to prior art half-rail differential logic circuits100A, but it also loaded the output nodes 111 and 113 of prior arthalf-rail differential logic circuit 100A and drew current from outputnodes 111 and 113 of prior art half-rail differential logic circuit 100Ato charge the control signals ein and {overscore (ein)}. In addition, inthe prior art, if prior art control circuit 100B were made small, thecontrol signals ein and {overscore (ein)} were slow, and this sloweddown the operation of prior art half-rail differential logic circuit100A. Consequently, there was pressure to increase the size of prior artcontrol circuit 100B. However, Increasing the size of prior art controlcircuit 100B to speed up the control signals ein and {overscore (ein)}also increased the loading on the output nodes 111 and 113 of prior arthalf-rail differential logic circuit 100A and therefore slowed down theevaluation of logic 123.

[0009] What is needed is a method and apparatus for creating half-raildifferential logic that does not require the complex control circuitryof prior art half-rail differential logic circuits and is thereforesimpler, more space efficient and is more reliable than prior arthalf-rail differential logic circuits.

SUMMARY OF THE INVENTION

[0010] According to the invention, the prior art control circuitry iseliminated. The clocked half-rail differential logic circuit of theinvention is instead activated from a delayed clock. According to theinvention, when clocked half-rail differential logic circuits of theinvention are cascaded together, a delayed clock is provided for eachclocked half-rail differential logic circuit of the invention. Eachdelayed clock is timed to at least the delay of the previous clockedhalf-rail differential logic circuit. Consequently, according to theinvention, a delay time is introduced to ensure each clocked half-raildifferential logic circuit of the invention is switched or “fired” onlyafter it has received an input from the previous clocked half-raildifferential logic circuit.

[0011] According to the invention, clocked half-rail differential logiccircuits do not require the significant additional components requiredin the prior art. This, in turn, means that the clocked half-raildifferential logic circuits of the invention require less space, aresimpler and have fewer components to potentially fail. In addition,clocked half-rail differential logic circuits of the invention eliminatethe loading of the output nodes of the half-rail differential logiccircuit since there are no control signals ein and {overscore (ein)},and therefore no prior art control circuits to draw current from theoutput nodes to charge the control signals ein and {overscore (ein)}.Consequently, using the clocked half-rail differential logic circuits ofthe invention, speed is increased because there is less loading on theoutput nodes and the clocked half-rail differential logic circuit of theinvention can start evaluating once a differential voltage developsbetween the complementary inputs coming from the previous clockedhalf-rail differential logic circuit.

[0012] In particular, one embodiment of the invention is a cascadedchain of clocked half-rail differential logic circuits. The chainincludes a first clocked half-rail differential logic circuit. The firstclocked half-rail differential logic circuit includes: a first clockedhalf-rail differential logic circuit clock input terminal; at least onefirst clocked half-rail differential logic circuit data input terminal;and at least one first clocked half-rail differential logic circuit dataoutput terminal.

[0013] The cascaded chain also includes a second clocked half-raildifferential logic circuit. The second clocked half-rail differentiallogic circuit includes: a second clocked half-rail differential logiccircuit clock input terminal; at least one second clocked half-raildifferential logic circuit data input terminal; and at least one secondclocked half-rail differential logic circuit data output terminal.

[0014] According to the invention, the at least one first clockedhalf-rail differential logic circuit data output terminal is coupled tothe at least one second clocked half-rail differential logic circuitdata input terminal to form the chain. According to the invention, afirst clock signal is coupled to the first clocked half-raildifferential logic circuit clock input terminal and a second clocksignal is coupled to the second clocked half-rail differential logiccircuit clock input terminal. According to the invention, the secondclock signal is delayed with respect to the first clock signal by apredetermined delay time.

[0015] In one embodiment of the invention, a delay circuit is coupledbetween the first clocked half-rail differential logic circuit clockinput terminal and the second clocked half-rail differential logiccircuit clock input terminal to provide the predetermined delay time.

[0016] One embodiment of the invention is a clocked half-raildifferential logic circuit that includes a clocked half-raildifferential logic circuit out terminal and a clocked half-raildifferential logic circuit out-not terminal.

[0017] The clocked half-rail differential logic circuit also includes afirst transistor including a first transistor first flow electrode, afirst transistor second flow electrode and a first transistor controlelectrode. The first transistor first flow electrode is coupled to afirst supply voltage.

[0018] The clocked half-rail differential logic circuit also includes asecond transistor, the second transistor including a second transistorfirst flow electrode, a second transistor second flow electrode and asecond transistor control electrode. The first transistor second flowelectrode is coupled to the second transistor first flow electrode andthe second transistor second flow electrode is coupled to the clockedhalf-rail differential logic circuit out terminal.

[0019] The clocked half-rail differential logic circuit also includes athird transistor, the third transistor including a third transistorfirst flow electrode, a third transistor second flow electrode and athird transistor control electrode. The first transistor second flowelectrode is coupled to the third transistor first flow electrode andthe third transistor second flow electrode is coupled to the clockedhalf-rail differential logic circuit out-not terminal.

[0020] The clocked half-rail differential logic circuit also includes afourth transistor, the fourth transistor including a fourth transistorfirst flow electrode, a fourth transistor second flow electrode and afourth transistor control electrode. The second transistor controlelectrode is coupled to the fourth transistor first flow electrode andthe clocked halfrail differential logic circuit out-not terminal. Thethird transistor control electrode is coupled to the fourth transistorsecond flow electrode and the clocked half-rail differential logiccircuit out terminal.

[0021] The clocked half-rail differential logic circuit also includes alogic block, the logic block including a logic block first inputterminal, a logic block second input terminal, a logic block outterminal, a logic block out-not terminal and a logic block fifthterminal. The logic block out terminal is coupled to the clockedhalf-rail differential logic circuit out terminal and the logic blockout-not terminal is coupled to the clocked half-rail differential logiccircuit out-not terminal.

[0022] The clocked half-rail differential logic circuit also includes afifth transistor, the fifth transistor including a fifth transistorfirst flow electrode, a fifth transistor second flow electrode and afifth transistor control electrode. The fifth transistor first flowelectrode is coupled to the logic block fifth terminal and the fifthtransistor second flow electrode is coupled to a second supply voltage.

[0023] A clock signal is coupled to the fifth transistor controlelectrode of the fifth transistor of the clocked half-rail differentiallogic circuit. A clock-not signal is coupled to the first transistorcontrol electrode of the first transistor of the clocked half-raildifferential logic circuit and the fourth transistor control electrodeof the fourth transistor of the clocked half-rail differential logiccircuit.

[0024] As discussed in more detail below, the method and apparatus ofthe invention for creating clocked half-rail differential logic does notrequire the complex control circuitry of prior art half-raildifferential logic circuits and is therefore simpler, saves space and ismore reliable than prior art half-rail differential logic circuits. As aresult, the clocked half-rail differential logic circuits of theinvention are better suited to the present electronics market thatstresses portability, compact size, lightweight and the capability forprolonged remote operation.

[0025] It is to be understood that both the foregoing generaldescription and following detailed description are intended only toexemplify and explain the invention as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings, which are incorporated in, andconstitute a part of this specification, illustrate embodiments of theinvention and, together with the description, serve to explain theadvantages and principles of the invention. In the drawings:

[0027]FIG. 1 shows a schematic diagram of a prior art half-raildifferential logic circuit and associated prior art control circuit asset forth in FIG. 1 of the 1997 IEEE International Solid-State CircuitsConference Paper ISSC97/SESSION 25/PROCESSORS AND LOGIC/PAPER 25.6;

[0028]FIG. 2 shows a schematic diagram of one embodiment of a clockedhalf-rail differential logic circuit designed according to theprinciples of the present invention;

[0029]FIG. 3 shows one embodiment of a cascaded chain of clockedhalf-rail differential logic circuits according to the principles of thepresent invention;

[0030]FIG. 4 is a one embodiment of a timing diagram for the cascadedchain of clocked half-rail differential logic circuits of the inventionshown in FIG. 3;

[0031]FIG. 5 shows a schematic diagram of one embodiment of a clockedhalf-rail differential logic circuit designed according to theprinciples of the present invention that includes an inverter as thedifferential logic.

DETAILED DESCRIPTION

[0032] The invention will now be described in reference to theaccompanying drawings. The same reference numbers may be used throughoutthe drawings and the following description to refer to the same or likeparts.

[0033] According to the invention, the prior art control circuitry (100Bin FIG. 1) is eliminated and the clocked half-rail differential logiccircuits (200 in FIG. 2, 300A, 300B, 300C and 300N in FIGS. 3 and 500 inFIG. 5) of the invention are activated instead from a delayed clocksignal (CLKA 361, CLKB 371, CLKC 381 and CLKN 391 in FIG. 3 and CLKA461, CLKB 471, CLKC 481 and CLKD 490 in FIG. 4).

[0034] According to the invention, when clocked half-rail differentiallogic circuits of the invention are cascaded together in a chain (301 inFIG. 3), a delayed clock signal is provided for each clocked half-raildifferential logic circuit of the invention (300A, 300B, 300C and 300Nin FIG. 3). The delayed clock signals are, according to the invention,timed to at least the delay of the previous clocked half-raildifferential logic circuit. Consequently, according to the invention, adelay circuit (363, 373, 383 in FIG. 3) introduces a delay time (463,473, and 483 in FIG. 4) between each clocked half-rail differentiallogic circuit of the invention to introduce a delay time and ensure eachclocked half-rail differential logic circuit of the invention isswitched or “fired” only after it has received an input from theprevious clocked half-rail differential logic circuit.

[0035] According to the invention, clocked half-rail differential logiccircuits do not require the significant additional components requiredin the prior art (control circuit 100B in FIG. 1). This, in turn, meansthat clocked half-rail differential logic circuits of the inventionrequire less space, are simpler and have fewer components to potentiallyfail. In addition, clocked half-rail differential logic circuits of theinvention also eliminate the loading of the output nodes (211 and 213 inFIG. 2, 311A, 313A, 311B, 313B, 311C, 313C, 311N and 313N in FIGS. 3 and511 and 513 in FIG. 5) of the half-rail differential logic circuit sincethere are no control signals (ein and {overscore (ein)} in FIG. 1) andno prior art control circuits (100B in FIG. 1) to draw current from theoutput nodes to charge the control signals. Consequently, using theclocked half-rail differential logic circuits of the invention, speed isincreased because there is less loading on the output nodes and theclocked half-rail differential logic circuits of the invention can startevaluating as soon as a differential voltage develops between thecomplementary inputs coming from the previous clocked half-raildifferential logic circuit.

[0036] As a result, the clocked half-rail differential logic circuits ofthe invention are better suited to the present electronics market thatstresses portability, compact size, lightweight and the capability forprolonged remote operation.

[0037]FIG. 2 shows a schematic diagram of one embodiment of a clockedhalf-rail differential logic circuit 200 designed according to theprinciples of the present invention. As seen in FIG. 2, according to theinvention, a clock signal CLK is coupled to an input node 232 of a clockinverter 234 to yield a clock-not signal {overscore (CLK)} at outputnode 236 of clock inverter 234.

[0038] As also seen in FIG. 2, clocked half-rail differential logiccircuit 200 includes a first supply voltage 202 coupled to a source, orfirst flow electrode 230, of a PFET 201. The signal {overscore (CLK)} iscoupled to a control electrode or gate 203 of first PFET 201 and acontrol electrode or gate 229 of a first NFET 209. A drain, or secondflow electrode 204, of first PFET 201 is coupled to both a source, orfirst flow electrode 206, of a second PFET 205 and a source, or firstflow electrode 208, of a third PFET 207. A control electrode or gate 216of second PFET 205 is coupled to a first flow electrode 240 of firstNFET 209 and an out-not terminal 213. A control electrode or gate 214 ofthird PFET 207 is coupled to a second flow electrode 238 of first NFET209 and an out terminal 211. A drain, or second flow electrode 210, ofsecond PFET 205 is coupled to out terminal 211 and a drain, or secondflow electrode 212, of third PFET 207 is coupled to out-not terminal213.

[0039] Out terminal 211 is coupled to a first terminal 218 of a logicblock 223 and out-not terminal 213 is coupled to a second terminal 220of logic block 223. Logic block 223 includes any type of differentiallogic and/or circuitry used in the art including various logic gates,logic devices and circuits. Logic block 223 also includes first andsecond input terminals 251 and 253 that, as discussed in more detailbelow, are typically coupled to an out and out-not terminal of aprevious clocked half-rail differential logic circuit stage (not shown).

[0040] Logic block 223 also includes third terminal 222 coupled to adrain, or first flow electrode 224, of a second NFET 225. A gate orcontrol electrode 227 of second NFET 225 is coupled to the signal CLKand a source, or second flow electrode 226, of second NFET 225 iscoupled to a second supply voltage 228.

[0041] A particular embodiment of a clocked half-rail differential logiccircuit 200 according to the invention is shown in FIG. 2. Those ofskill in the art will recognize that clocked half-rail differentiallogic circuit 200 can be easily modified. For example, differenttransistors, i.e., first, second and third PFETs 201, 205 and 207 orfirst and second NFETs 209 and 225 can be used. In particular, the NFETsand PFETS shown in FIG. 2 can be readily exchanged for PFETs and NFETsby reversing the polarities of the supply voltages 202 and 228, or byother well known circuit modifications. Consequently, the clockedhalf-rail differential logic circuit 200 that is shown in FIG. 2 issimply one embodiment of the invention used for illustrative purposesonly and does not limit the present invention to that one embodiment ofthe invention.

[0042] Clocked half-rail differential logic circuit 200 has two modes,or phases, of operation; a pre-charge phase and an evaluation phase. Inone embodiment of a clocked half-rail differential logic circuit 200according to the invention, in the pre-charge phase, the signal CLK islow or a digital “0” and the signal {overscore (CLK)} is high or adigital “1”. Consequently, first PFET 201 and second NFET 225 are notconducting or are “off” and logic block 223 is isolated from firstsupply voltage 202 and second supply voltage 228. In addition, duringthe pre-charge phase, first NFET 209 is conducting or is “on” and,therefore, out terminal 211 is shorted to out-not terminal 213.Consequently, the supply voltage to logic block 223 is approximatelyhalf the supply voltage 202, i.e., for a first supply voltage 202 of Vddand a second supply voltage 228 of ground, logic block 223 operates ataround Vdd/2. During pre-charge, second and third PFETs 205 and 207 aretypically not performing any function.

[0043] In one embodiment of a clocked half-rail differential logiccircuit 200 according to the invention, in the evaluation phase, thesignal CLK is high or a digital “1” and the signal {overscore (CLK)} islow or a digital “0”. Consequently, first PFET 201 and second NFET 225are conducting or are “on” and first NFET 209 is not conducting or is“off”. Consequently, depending on the particular logic in logic block223, either second PFET 205, or third PFET 207, is conducting or is “on”and the other of second PFET 205, or third PFET 207, is not conductingor is “off”. As a result, either out terminal 211 goes fromapproximately half first supply voltage 202 to approximately secondsupply voltage 228 or out-not terminal 213 goes from approximately halffirst supply voltage 202 to approximately first supply voltage 202,i.e., for a first supply voltage 202 of Vdd and a second supply voltage228 of ground, out terminal 211 goes from approximately Vdd/2 to zeroand out-not terminal 213 goes from approximately Vdd/2 to Vdd.

[0044] As discussed above, the method and apparatus of the invention forcreating clocked half-rail differential logic circuits 200 does notrequire the complex control circuit 100B (FIG. 1) of prior art half-raildifferential logic circuits 100A and is therefore simpler, saves spaceand is more reliable than prior art half-rail differential logiccircuits 100A. As a result, the clocked half-rail differential logiccircuits 200 (FIG. 2) of the invention are better suited to the presentelectronics market that stresses portability, compact size, lightweightand the capability for prolonged remote operation. However, as alsodiscussed above, according to the invention, when clocked half-raildifferential logic circuits 200 of the invention are cascaded togetherin a chain, a delayed clock signal must be provided for each clockedhalf-rail differential logic circuit 200 of the invention. The delayedclock signals are, according to the invention, timed to be at least thedelay of the previous clocked half-rail differential logic circuit 200to ensure each clocked half-rail differential logic circuit 200 of theinvention is switched or “fired” only after it has received an inputfrom the previous clocked half-rail differential logic circuit 200.

[0045]FIG. 3 shows one embodiment of a cascaded chain 301 of clockedhalf-rail differential logic circuits 300A, 300B 300C and 300N of thepresent invention. Each clocked half-rail differential logic circuit300A, 300B, 300C and 300N represents a stage in cascaded chain 301. Inone embodiment of the invention, each clocked half-rail differentiallogic circuit 300A, 300B 300C and 300N is identical to clocked half-raildifferential logic circuit 200 discussed above with respect to FIG. 2.

[0046] As seen in FIG. 3, clocked half-rail differential logic circuit300A includes: a clock input terminal 327A; an out terminal 311A; and anoutput-not terminal 313A. Clocked half-rail differential logic circuit300B includes: a clock input terminal 327B; an input terminal 351B,coupled to output terminal 311A of clocked half-rail differential logiccircuit 300A; an input-not terminal 353B, coupled to output-not terminal313A of clocked half-rail differential logic circuit 300A; an outputterminal 311B; and an output-not terminal 313A. Likewise, clockedhalf-rail differential logic circuit 300C includes: a clock inputterminal 327C; an input terminal 351C, coupled to output terminal 311Bof clocked half-rail differential logic circuit 300B; an input-notterminal 353C, coupled to output-not terminal 313B of clocked half-raildifferential logic circuit 300B; an output terminal 311C; and anoutput-not terminal 313C. Clocked half-rail differential logic circuit300N includes: a clock input terminal 327N; an input terminal 351N,coupled to an output terminal 311N−1 (not shown) of a clocked half-raildifferential logic circuit 300N−1 (not shown); an input-not terminal353N, coupled to an output-not terminal 313N−1 (not shown) of a clockedhalf-rail differential logic circuit 300N−1 (not shown); an outputterminal 311N; and an output-not terminal 313N.

[0047] According to the invention, any number of clocked half-raildifferential logic circuits 300A, 300B, 300C and 300N can be employedwith cascaded chain 301. As also shown in FIG. 3, and discussed above,output terminal 311A of clocked half-rail differential logic circuit300A couples signal OUTA to input terminal 351B of clocked half-raildifferential logic circuit 300B and output-not terminal 313A of clockedhalf-rail differential logic circuit 300A couples signal {overscore(OUTA)} to input-not terminal 353B of clocked half-rail differentiallogic circuit 300B. Likewise, output terminal 311B of clocked half-raildifferential logic circuit 300B couples signal OUTB to input terminal351C of clocked half-rail differential logic circuit 300C and output-notterminal 313B of clocked half-rail differential logic circuit 300Bcouples signal {overscore (OUTB)} to input-not terminal 353C of clockedhalf-rail differential logic circuit 300C. In addition, output terminal311N of clocked half-rail differential logic circuit 300N couples signalOUTN to an input terminal 351N+1 (not shown) of a clocked half-raildifferential logic circuit 300N+1 (not shown) and output-not terminal313N of clocked half-rail differential logic circuit 300N couples signal{overscore (OUTN)} to an input-not terminal 353N+1 (not shown) of aclocked half-rail differential logic circuit 300N+1 (not shown).

[0048] In addition to the structure discussed above, according to theinvention, each clocked half-rail differential logic circuit 300A, 300B,300C and 300N of cascaded chain 301 receives its own delayed clocksignal CLKA 361, CLKB 371, CLKC 381 and CLKN 391, respectively.According to the invention clock signals CLKA 361, CLKB 371, CLKC 381and CLKN 391 are provided to clocked half-rail differential logiccircuit 300A, 300B, 300C and 300N, respectively, by introducing delaycircuits 363, 373, 383 and 393 between successive clocked half-raildifferential logic circuits 300A, 300B, 300C and 300N. Consequently,delay circuit 363 introduces a delay time between signal CLKA 361,coupled to clock input terminal 327A of clocked half-rail differentiallogic circuit 300A, and signal CLKB 371, coupled to clock input terminal327B of clocked half-rail differential logic circuit 300B. Delay circuit373 introduces a delay time between signal CLKB 371 and signal CLKC 381,coupled to clock input terminal 327C of clocked half-rail differentiallogic circuit 300C. Two delay circuits 363 and 373 introduce two delaytimes between signal CLKA 361 and signal CLKC 381. Likewise, a series ofN−1 delay circuits, and N−1 delay times, exists between signal CLKA 361and signal CLKN 391, coupled to clock input terminal 327N of clockedhalf-rail differential logic circuit 300N, and a further delay circuit393 introduces a further delay time between CLKN 391 and CLCK N+1 (notshown) coupled to a clock input terminal 327N+1 (not shown) of a clockedhalf-rail differential logic circuit 300N+1 (not shown).

[0049] Delay circuits 363, 373, 383 and 393 are any one of many delaycircuits known in the art such as inverters, or groups of inverters,gates, transistors or any other elements that introduce a time delay.According to the invention, delay circuits 363, 373, 383 and 393 areused to ensure the activation of each stage, i.e., each clockedhalf-rail differential logic circuit 300A, 300B, 300C and 300N, is timedsuch that the delay of the clock is longer than the evaluation durationof the previous stage. In one embodiment of the invention, the delayedclock signals CLKA 361, CLKB 371, CLKC 381 and CLKN 391 are timed toswitch high (active) when the differential input voltage to clockedhalf-rail differential logic circuit 300A, 300B, 300C and 300N reaches apredetermined voltage level. The clock delay can be adjusted accordingto the predetermined differential voltage level required for robustnessand the specific needs of the circuit designer. This differentialvoltage level is typically a function of process and will vary fromcircuit to circuit and system to system. Importantly, however, using themethod and structure of the invention, there is no need for the controlsignals ein and {overscore (ein)} or control circuit 100B (FIG. 1).

[0050]FIG. 4 is one embodiment of a timing diagram for cascaded chain301 of clocked half-rail differential logic circuits 300A, 300B, 300Cand 300N of FIG. 3. As seen in FIG. 3 and FIG. 4 together, according toone embodiment of the invention, at time TO, i.e., point 400A in FIG. 4,signal CLKA 461 goes high. After a short switching delay 466, such asthe short switching delay inherent in any circuit, signal OUTA 411A atoutput terminal 311A switches high and signal {overscore (OUTA)} atoutput-not terminal 313A switches low at points 467 and 469,respectively. A delay time 463 from point T0 400A and to point T1 400Bis introduced by delay circuit 363. As discussed above, delay time 463helps ensure clocked half-rail differential logic circuit 300B receivessignals OUTA and {overscore (OUTA)} from clocked half-rail differentiallogic circuit 300A before the switching of signal CLKB 471.

[0051] At point 472 in FIG. 4, i.e., at point T1 400B, signal CLKB 471switches high. After a short switching delay 476, signal OUTB 411B atoutput terminal 311B switches high and signal {overscore (OUTA)} atoutput-not terminal 313B switches low at points 477 and 479,respectively. A delay time 473 from point T1 400B to point T2 400C isintroduced by delay circuit 373. As discussed above, delay time 473helps ensure clocked half-rail differential logic circuit 300C receivessignals OUTB and {overscore (OUTB)} from clocked half-rail differentiallogic circuit 300B before the switching of signal CLKC 481.

[0052] At point 482 in FIG. 4, i.e., at point T2 400C, signal CLKC 481switches high. After a short switching delay 486, signal OUTC 411C atoutput terminal 311C switches high and signal {overscore (OUTA)} atoutput-not terminal 313C switches low at points 487 and 489,respectively. A delay time 483 from point T2 400C to point T3 400D isintroduced by delay circuit 383. As discussed above, delay time 483helps ensure the following clocked half-rail differential logic circuit(not shown) receives signals OUTC and {overscore (OUTC)} from clockedhalf-rail differential logic circuit 300C before the switching of signalCLKD 490.

[0053] At point 492 in FIG. 4, i.e., at point T3 400D, signal CLKD 491switches high. As discussed above, according to the invention, anynumber of clocked half-rail differential logic circuits 300A, 300B, 300Cand 300N can be employed with cascaded chain 301. In addition, theprocess discussed above will repeat for each switching of the systemclock. Those of skill in the art will further recognize that the choiceof signal highs and signal lows was made arbitrarily in FIG. 4 forillustrative purposes only and that at other times, and in otherembodiments of the invention, signal highs could be replaced with signallows and vice-versa.

[0054]FIG. 5 shows a schematic diagram of one embodiment of a clockedhalf-rail differential logic circuit 500 designed according to theprinciples of the present invention that includes an inverter 523. Asseen in FIG. 5, according to the invention, a clock signal CLK iscoupled to an input node 532 of a clock inverter 534 to yield aclock-not signal CLK at output node 536 of clock inverter 534.

[0055] As also seen in FIG. 5, clocked half-rail differential logiccircuit 500 includes a first supply voltage 502 coupled to a source, orfirst flow electrode 530, of a PFET 501. The signal {overscore (CLK)} iscoupled to a control electrode or gate 503 of first PFET 501 and acontrol electrode or gate 529 of a first NFET 509. A drain, or secondflow electrode 504, of first PFET 501 is coupled to both a source, orfirst flow electrode 506, of a second PFET 505 and a source, or firstflow electrode 508, of a third PFET 507. A control electrode or gate 516of second PFET 505 is coupled to a first flow electrode 540 of firstNFET 509 and an out-not terminal 513. A control electrode or gate 514 ofthird PFET 507 is coupled to a second flow electrode 538 of first NFET509 and an out terminal 511. A drain, or second flow electrode 510, ofsecond PFET 505 is coupled to out terminal 511 and a drain, or secondflow electrode 512, of third PFET 507 is coupled to out-not terminal513.

[0056] Out terminal 511 is coupled to a drain, or first flow electrode518, of a first inverter NFET 561 and out-not terminal 513 is coupled toa drain, or first flow electrode 520, of a second inverter NFET 563. Agate or control electrode 551 of first inverter NFET 561 is coupled toreceive an IN signal, typically from a previous stage in a cascadechain, such as cascade chain 301 discussed above, and a gate or controlelectrode 553 of second inverter NFET 563 is coupled to receive an{overscore (IN)} signal, also typically from a previous stage in acascade chain, such as cascade chain 301 discussed above. The sources,or second flow electrodes 542 and 546, of first inverter NFET 561 andsecond inverter NFET 563, respectively, are coupled and to a junction522.

[0057] Junction 522 is coupled to a drain, or first flow electrode 524,of a second NFET 525. A gate or control electrode 527 of second NFET 525is coupled to the signal CLK and a source, or second flow electrode 526,of second NFET 525 is coupled to a second supply voltage 528.

[0058] A particular embodiment of a clocked half-rail differential logiccircuit 500 according to the invention is shown in FIG. 5. Those ofskill in the art will recognize that clocked half-rail differentiallogic circuit 500 can be easily modified. For example, differenttransistors, i.e., first, second and third PFETs 501, 505 and 507 orfirst and second NFETs 509 and 525 can be used. In particular, the NFETsand PFETS shown in FIG. 5 can be readily exchanged for PFETs and NFETsby reversing the polarities of the supply voltages 502 and 528, or byother well known circuit modifications. Consequently, the clockedhalf-rail differential logic circuit 500 that is shown in FIG. 5 issimply one embodiment of the invention used for illustrative purposesonly and does not limit the present invention to that one embodiment ofthe invention.

[0059] As with clocked half-rail differential logic circuit 200,discussed above with respect to FIG. 2, clocked half-rail differentiallogic circuit 500 has two modes, or phases, of operation; a pre-chargephase and an evaluation phase. In one embodiment of a clocked half-raildifferential logic circuit 500 according to the invention, in thepre-charge phase, the signal CLK is low or a digital “0” and the signal{overscore (CLK)} is high or a digital “1”. Consequently, first PFET 501and second NFET 525 are not conducting or are “off” and inverter 523 isisolated from first supply voltage 502 and second supply voltage 528. Inaddition, during this pre-charge phase, first NFET 509 is conducting oris “on” and, therefore, out terminal 511 is shorted to out-not terminal513. Consequently, the supply voltage to inverter 523 is approximatelyhalf the supply voltage 502, i.e., for a first supply voltage 502 of Vddand a second supply voltage 528 of ground, inverter 523 operates ataround Vdd/2. During pre-charge, second and third PFETs 505 and 507 aretypically not performing any function.

[0060] In one embodiment of a clocked half-rail differential logiccircuit 500 according to the invention, in the evaluation phase, thesignal CLK is high or a digital “1” and the signal {overscore (CLK)} islow or a digital “0”. Consequently, first PFET 501 and second NFET 525are conducting or are “on” and first NFET 509 is not conducting or is“off”. Consequently, depending on the particular logic in logic block523, either second PFET 505, or third PFET 507, is conducting or is “on”and the other of second PFET 505, or third PFET 507, is not conductingor is “off”. As a result, either out terminal 511 goes fromapproximately half first supply voltage 502 to approximately secondsupply voltage 528 or out-not terminal 513 goes from approximately halffirst supply voltage 502 to approximately first supply voltage 502,i.e., for a first supply voltage 502 of Vdd and a second supply voltage528 of ground, out terminal 511 goes from about Vdd/2 to zero andout-not terminal 513 goes from about Vdd/2 to Vdd.

[0061] When signal IN at gate 551 of first inverter NFET 561 is low,first inverter NFET 561 does not conduct and signal OUT at out terminal511 is high. When signal IN at gate 551 of first inverter NFET 561 ishigh, first inverter NFET 561 conducts and signal OUT at out terminal511 is low. Likewise, when signal {overscore (IN)} at gate 553 of secondinverter NFET 563 is low, i.e., when signal IN at gate 551 of firstinverter NFET 561 is high, second inverter NFET 563 does not conduct andsignal {overscore (OUT)} at out-not terminal 513 is high. When signal{overscore (IN)} at gate 553 of second inverter NFET 563 is high, firstinverter NFET 563 conducts and signal {overscore (OUT)} at out-notterminal 513 is low. Consequently, Inverter 523 of clocked half-raildifferential logic circuit 500 in FIG. 5 produces the expected180-degree polarity shift.

[0062] As shown above, according to the invention, the prior art controlcircuitry is eliminated and the clocked half-rail differential logiccircuits of the invention are activated instead from a delayed clocksignal. According to the invention, when clocked half-rail differentiallogic circuits of the invention are cascaded together in a chain, adelayed clock signal is provided for each clocked half-rail differentiallogic circuit of the invention. The delayed clock signals are, accordingto the invention, timed to be at least the delay of the previous clockedhalf-rail differential logic circuit. Consequently, according to theinvention, a delay time is introduced to ensure each clocked half-raildifferential logic circuit of the invention is switched or “fired” onlyafter it has received an input from the previous clocked half-raildifferential logic circuit stage.

[0063] According to the invention, clocked half-rail differential logiccircuits do not require the significant additional components requiredin the prior art. This, in turn, means that clocked half-raildifferential logic circuits of the invention require less space, aresimpler to implement and employ and have fewer components to potentiallyfail. In addition, clocked half-rail differential logic circuits of theinvention also eliminate the loading of the output nodes of thehalf-rail differential logic circuit since there are no control signals,and no prior art control circuits, to draw current from the output nodesto charge the control signals. Consequently, using the clocked half-raildifferential logic circuits of the invention, speed is increased becausethere is less loading on the output nodes and the clocked half-raildifferential logic circuits of the invention can start evaluating assoon as a differential voltage develops between the complementary inputscoming from the previous clocked half-rail differential logic circuit.

[0064] As a result, the clocked half-rail differential logic circuits ofthe invention are better suited to the present electronics market thatstresses portability, compact size, lightweight and the capability forprolonged remote operation.

[0065] The foregoing description of an implementation of the inventionhas been presented for purposes of illustration and description only,and therefore is not exhaustive and does not limit the invention to theprecise form disclosed. Modifications and variations are possible inlight of the above teachings or may be acquired from practicing theinvention.

[0066] For example, for illustrative purposes specific embodiments ofthe invention were shown with specific transistors. However, the NFETsand PFETS shown in the figures can be readily exchanged for PFETs andNFETs by reversing the polarities of the supply voltages or by otherwell known circuit modifications.

[0067] Consequently, the scope of the invention is defined by the claimsand their equivalents.

What is claimed is:
 1. A cascaded chain of clocked half-raildifferential logic circuits, said chain comprising: a first clockedhalf-rail differential logic circuit, said first clocked half-raildifferential logic circuit comprising: a first clocked half-raildifferential logic circuit clock input terminal; at least one firstclocked half-rail differential logic circuit data input terminal; and atleast one first clocked half-rail differential logic circuit data outputterminal; a second clocked half-rail differential logic circuit, saidsecond clocked half-rail differential logic circuit comprising: a secondclocked half-rail differential logic circuit clock input terminal; atleast one second clocked half-rail differential logic circuit data inputterminal; and at least one second clocked half-rail differential logiccircuit data output terminal; a first clock signal coupled to said firstclocked half-rail differential logic circuit clock input terminal; and asecond clock signal coupled to said second clocked half-raildifferential logic circuit clock input terminal, wherein; said at leastone first clocked half-rail differential logic circuit data outputterminal is coupled to said at least one second clocked half-raildifferential logic circuit data input terminal, further wherein; saidsecond clock signal is delayed with respect to said first clock signalby a predetermined delay time.
 2. The chain of claim 1 furthercomprising: a delay circuit coupled between said first clocked half-raildifferential logic circuit clock input terminal and said second clockedhalf-rail differential logic circuit clock input terminal for providingsaid predetermined delay time.
 3. The chain of claim 2, wherein; saiddelay circuit comprises at least one inverter.
 4. The chain of claim 2,wherein; said delay circuit comprises at least two inverters.
 5. Acascaded chain of clocked half-rail differential logic circuits, saidchain comprising: a first supply voltage; a second supply voltage; afirst clocked half-rail differential logic circuit, said first clockedhalf-rail differential logic circuit comprising: a first clockedhalf-rail differential logic circuit out terminal; a first clockedhalf-rail differential logic circuit out-not terminal; a firsttransistor, said first transistor comprising a first transistor firstflow electrode, a first transistor second flow electrode and a firsttransistor control electrode, said first supply voltage being coupled tosaid first transistor first flow electrode; a second transistor, saidsecond transistor comprising a second transistor first flow electrode, asecond transistor second flow electrode and a second transistor controlelectrode, said first transistor second flow electrode being coupled tosaid second transistor first flow electrode, said second transistorsecond flow electrode being coupled to said first clocked half-raildifferential logic circuit out terminal; a third transistor, said thirdtransistor comprising a third transistor first flow electrode, a thirdtransistor second flow electrode and a third transistor controlelectrode, said first transistor second flow electrode being coupled tosaid third transistor first flow electrode, said third transistor secondflow electrode being coupled to said first clocked half-raildifferential logic circuit out-not terminal; a fourth transistor, saidfourth transistor comprising a fourth transistor first flow electrode, afourth transistor second flow electrode and a fourth transistor controlelectrode, said second transistor control electrode being coupled tosaid fourth transistor first flow electrode and said first clockedhalf-rail differential logic circuit out-not terminal, said thirdtransistor control electrode being coupled to said fourth transistorsecond flow electrode and said first clocked half-rail differentiallogic circuit out terminal; a logic block, said logic block comprising alogic block first input terminal, a logic block second input terminal, alogic block out terminal, a logic block out-not terminal and a logicblock fifth terminal, said logic block out terminal being coupled tosaid first clocked half-rail differential logic circuit out terminal,said logic block out-not terminal being coupled to said first clockedhalf-rail differential logic circuit out-not terminal; a fifthtransistor, said fifth transistor comprising a fifth transistor firstflow electrode, a fifth transistor second flow electrode and a fifthtransistor control electrode, said fifth transistor first flow electrodebeing coupled to said logic block fifth terminal, said fifth transistorsecond flow electrode being coupled to said second supply voltage; afirst clock signal, said first clock signal being coupled to said fifthtransistor control electrode of said fifth transistor of said firstclocked half-rail differential logic circuit; a first clock-not signal,said first clock-not signal being coupled to said first transistorcontrol electrode of said first transistor of said first clockedhalf-rail differential logic circuit and said fourth transistor controlelectrode of said fourth transistor of said first clocked half-raildifferential logic circuit; a second clocked half-rail differentiallogic circuit, said second clocked half-rail differential logic circuitcomprising: a second clocked half-rail differential logic circuit outterminal; a second clocked half-rail differential logic circuit out-notterminal; a first transistor, said first transistor comprising a firsttransistor first flow electrode, a first transistor second flowelectrode and a first transistor control electrode, said first supplyvoltage being coupled to said first transistor first flow electrode; asecond transistor, said second transistor comprising a second transistorfirst flow electrode, a second transistor second flow electrode and asecond transistor control electrode, said first transistor second flowelectrode being coupled to said second transistor first flow electrode,said second transistor second flow electrode being coupled to saidsecond clocked half-rail differential logic circuit out terminal; athird transistor, said third transistor comprising a third transistorfirst flow electrode, a third transistor second flow electrode and athird transistor control electrode, said first transistor second flowelectrode being coupled to said third transistor first flow electrode,said third transistor second flow electrode being coupled to said secondclocked half-rail differential logic circuit out-not terminal; a fourthtransistor, said fourth transistor comprising a fourth transistor firstflow electrode, a fourth transistor second flow electrode and a fourthtransistor control electrode, said second transistor control electrodebeing coupled to said fourth transistor first flow electrode and saidsecond clocked half-rail differential logic circuit out-not terminal,said third transistor control electrode being coupled to said fourthtransistor second flow electrode and said second clocked half-raildifferential logic circuit out terminal; a logic block, said logic blockcomprising a logic block first input terminal, a logic block secondinput terminal, a logic block out terminal, a logic block out-notterminal and a logic block fifth terminal, said logic block first inputterminal being coupled to said first clocked half-rail differentiallogic circuit out terminal, said logic block second input terminal beingcoupled to said first clocked half-rail differential logic circuitout-not terminal, said logic block out terminal being coupled to saidsecond clocked half-rail differential logic circuit out terminal, saidlogic block out-not terminal being coupled to said second clockedhalf-rail differential logic circuit out-not terminal; a fifthtransistor, said fifth transistor comprising a fifth transistor firstflow electrode, a fifth transistor second flow electrode and a fifthtransistor control electrode, said fifth transistor first flow electrodebeing coupled to said logic block fifth terminal, said fifth transistorsecond flow electrode being coupled to said second supply voltage; asecond clock signal, said second clock signal being coupled to saidfifth transistor control electrode of said fifth transistor of saidsecond clocked half-rail differential logic circuit; a second clock-notsignal, said second clock-not signal being coupled to said firsttransistor control electrode of said first transistor of said secondclocked half-rail differential logic circuit and said fourth transistorcontrol electrode of said fourth transistor of said second clockedhalf-rail differential logic circuit, wherein; said second clock signalis delayed with respect to said first clock signal by a predetermineddelay time and said second clock-not signal is delayed with respect tosaid first clock-not signal by said predetermined delay time.
 6. Thechain of claim 5, further comprising: a delay circuit; said delaycircuit coupled between said fifth transistor control electrode of saidfifth transistor of said first clocked half-rail differential logiccircuit and said fifth transistor control electrode of said fifthtransistor of said second clocked half-rail differential logic circuit;said delay circuit coupled between said first transistor controlelectrode of said first transistor of said first clocked half-raildifferential logic circuit and said first transistor control electrodeof said first transistor of said second clocked half-rail differentiallogic circuit; said delay circuit coupled between said fourth transistorcontrol electrode of said fourth transistor of said first clockedhalf-rail differential logic circuit and said fourth transistor controlelectrode of said fourth transistor of said second clocked half-raildifferential logic circuit; said delay circuit thereby providing saidpredetermined delay time.
 7. The chain of claim 6, wherein; said delaycircuit comprises at least one inverter.
 8. The chain of claim 6,wherein; said delay circuit comprises at least two inverters.
 9. Thechain of claim 1, wherein; said logic block of said first clockedhalf-rail differential logic circuit and said logic block of said secondclocked half-rail differential logic circuit comprise differentiallogic.
 10. The chain of claim 1, wherein; said logic block of said firstclocked half-rail differential logic circuit and said logic block ofsaid second clocked half-rail differential logic circuit comprisedifferential logic gates.
 11. The chain of claim 1, wherein; said logicblock of said first clocked half-rail differential logic circuit andsaid logic block of said second clocked half-rail differential logiccircuit comprise inverters.
 12. The chain of claim 1, wherein; saidfirst supply voltage is Vdd and said second supply voltage is ground.13. The chain of claim 12, wherein; said first transistor, said secondtransistor and said third transistor of said first clocked half-raildifferential logic circuit and said first transistor, said secondtransistor and said third transistor of said second clocked half-raildifferential logic circuit are PFETs.
 14. The chain of claim 13,wherein; said fourth transistor and said fifth transistor of said firstclocked half-rail differential logic circuit and said fourth transistorand said fifth transistor of said second clocked half-rail differentiallogic circuit are NFETs.
 15. A clocked half-rail differential logiccircuit, said clocked half-rail differential logic circuit comprising: aclocked half-rail differential logic circuit out terminal; a clockedhalf-rail differential logic circuit out-not terminal; a firsttransistor, said first transistor comprising a first transistor firstflow electrode, a first transistor second flow electrode and a firsttransistor control electrode, a first supply voltage being coupled tosaid first transistor first flow electrode; a second transistor, saidsecond transistor comprising a second transistor first flow electrode, asecond transistor second flow electrode and a second transistor controlelectrode, said first transistor second flow electrode being coupled tosaid second transistor first flow electrode, said second transistorsecond flow electrode being coupled to said clocked half-raildifferential logic circuit out terminal; a third transistor, said thirdtransistor comprising a third transistor first flow electrode, a thirdtransistor second flow electrode and a third transistor controlelectrode, said first transistor second flow electrode being coupled tosaid third transistor first flow electrode, said third transistor secondflow electrode being coupled to said clocked half-rail differentiallogic circuit out-not terminal; a fourth transistor, said fourthtransistor comprising a fourth transistor first flow electrode, a fourthtransistor second flow electrode and a fourth transistor controlelectrode, said second transistor control electrode being coupled tosaid fourth transistor first flow electrode and said clocked half-raildifferential logic circuit out-not terminal, said third transistorcontrol electrode being coupled to said fourth transistor second flowelectrode and said clocked half-rail differential logic circuit outterminal; a logic block, said logic block comprising a logic block firstinput terminal, a logic block second input terminal, a logic block outterminal, a logic block out-not terminal and a logic block fifthterminal, said logic block out terminal being coupled to said clockedhalf-rail differential logic circuit out terminal, said logic blockout-not terminal being coupled to said clocked half-rail differentiallogic circuit out-not terminal; a fifth transistor, said fifthtransistor comprising a fifth transistor first flow electrode, a fifthtransistor second flow electrode and a fifth transistor controlelectrode, said fifth transistor first flow electrode being coupled tosaid logic block fifth terminal, said fifth transistor second flowelectrode being coupled to a second supply voltage; a clock signal, saidclock signal being coupled to said fifth transistor control electrode ofsaid fifth transistor of said clocked half-rail differential logiccircuit; and a clock-not signal, said clock-not signal being coupled tosaid first transistor control electrode of said first transistor of saidclocked half-rail differential logic circuit and said fourth transistorcontrol electrode of said fourth transistor of said clocked half-raildifferential logic circuit.
 16. The clocked half-rail differential logiccircuit of claim 15, wherein; said logic block of said clocked half-raildifferential logic circuit comprises differential logic.
 17. The clockedhalf-rail differential logic circuit of claim 15, wherein; said logicblock of said clocked half-rail differential logic circuit comprisesdifferential logic gates.
 18. The clocked half-rail differential logiccircuit of claim 15, wherein; said logic block of said clocked half-raildifferential logic circuit comprises an inverter.
 19. The clockedhalf-rail differential logic circuit of claim 15, wherein; said firstsupply voltage is Vdd and said second supply voltage is ground.
 20. Theclocked half-rail differential logic circuit of claim 19, wherein; saidfirst transistor, said second transistor and said third transistor arePFETs.
 21. The clocked half-rail differential logic circuit of claim 20,wherein; said fourth transistor and said fifth transistor are NFETs.